The present invention relates to flash memory devices and, more particularly, to an erase method in which an erase operating time can be shortened and an erase operating characteristic can be improved.
Semiconductor memory devices include non-volatile memory devices whose data is not lost even if the supply of power is cut off. The non-volatile memory devices include the flash memory device. The flash memory device includes a NOR flash memory device and a NAND flash memory device. Of them, the NAND flash memory device includes a memory cell array with a plurality of memory cell blocks. An erase operation of the NAND flash memory device is performed on a memory-cell-block basis. In general, the erase operation of the NAND flash memory device is implemented by applying a voltage of 0 V to word lines connected to memory cells included in a selected block and applying a high voltage (e.g., 20 V) to the well region.
In the NAND flash memory device constructed above, an erase/writing (E/W) cycling characteristic must be guaranteed in order to prevent any problems from occurring (e.g., an electrical characteristic problem) even if write (program) and deletion (erase) operations are carried out repeatedly. If E/W cycling is repeated numerous times, electrons are trapped in the tunnel oxide layer, so that threshold voltages are influenced at the time of a program operation and an erase operation.
FIG. 1 is a graph illustrating the variation in threshold voltages with the number of repeated program operations and erase operations.
Referring to FIG. 1, as the number of the program operations and erase operations increases, a threshold voltage of a memory cell becomes higher than a target voltage. In other words, at the time of the program operation, the memory cell is programmed more rapidly than normal, so that the program operation is performed with the threshold voltage being higher than the target voltage (hereinafter, this will be referred to as a “fast program phenomena”). Further, at the time of the erase operation, the memory cell is discharged slower than normal, so that the erase operation is performed with the threshold voltage being higher than the target voltage (hereinafter, this will be referred to as a “slow erase phenomena”).
Thus, in order to overcome the higher threshold voltages the erase operation is carried out in such a manner that an erase voltage applied to a well region is raised as high as the increased threshold voltage, at the time of the erase operation. However, as the size of a cell shrinks, the area of the tunnel oxide layer is decreased, thereby further weakening the E/W cycling characteristic.
FIG. 2 is a graph illustrating variation in a fast program phenomenon and a slow erase phenomenon depending on erase voltages.
From FIG. 2, it can be seen that as an erase voltage applied to the well region is raised at the time of the erase operation, the fast program phenomenon and the slow erase phenomenon become profound. In other words, as the erase voltage rises, the fast program phenomenon becomes profound, so that the threshold voltage after the program operation is even higher than a target voltage. Furthermore, at the time of the erase operation, the slow erase phenomenon also becomes profound, so that the threshold voltage after the erase operation is even higher than the target voltage. As described above, the fast program phenomenon or the slow erase phenomenon is sensitive to the level of the erase voltage. It makes it difficult to use a high erase voltage.
Accordingly, in order to prevent the phenomena, at the time of a first erase operation, the erase operation can be performed by gradually increasing the voltage difference between the control gate and the well region after starting with a low voltage difference. This erase operation includes an Incremental Stepping Pulse Erase (ISPE) method which increases the erase voltage applied to the well region from a low voltage to a high voltage, and a Decreasing Stepping Pulse Erase (DSPE) method which reduces the voltage applied to the control gate from a high voltage to a low voltage. The methods can improve the E/W cycling characteristic by incrementally increasing the voltage difference after starting with a low voltage difference between the control gate and the well region. However, these erase methods have the following problems.
First, since the erase operation is repeated several times while increasing the voltage difference between the control gate and the well region, an overall erase operating time increases.
Next, if the voltage difference between the control gate and the well region is increased so as to reduce the erase operating time, the E/W cycling characteristic will deteriorate.